Analysis of Berger Code Based Fault Tolerant Techniques for Embedded System

With continued scaling of silicon process technology, producing reliable electronic components in extremely denser technologies pose a challenge. Further, the systems fabricated in deep sub-micron technology are prone to intermittent or transient faults, causing unidirectional errors, upon exposure to ionizing radiations during system operation. The ability to operate in the intended manner even in the presence of faults is an important objective of all electronic systems. In order to achieve fault-tolerance, each module of the system must be fault-tolerant by possessing run-time (or online) fault detection capabilities. Totally Self-checking (TSC) circuits permit online detection of hardware faults. The objective of this project is to analyze the area (resource utilization), speed and power consumption for n bit Look-Up Table (LUT) implementation with and without fault detection capability using Berger technique on Xilinx FPGA. The Berger code is the least redundant systematic code available for detecting all single and multi-bit unidirectional errors. This project is proposed to find the fault in 4, 8, 16, 32 bits LUT. The fault will be detected by Berger checker architecture.